Open Silicon Announces The World's First HMC 2.0 Controller IP - Partners Include Altera and Intel
Open up-Silicon recently announced the HMC 2.0 (Memory) Controller IP and known partners (not listed in the Press Release) such as Intel are going to be implementing the new blueprint in their future semi conductor products. This latest standard (HMC 2.0) will probably be featured in Intel's Xeon Phi and certain Altera FPGA/SoCs.
A slide from Altera showing HMC integration into FPGAs and SoCs @Altera Public Domain
HMC 2.0 Controller IP released past Open-Silicon - to be implemented past the HMC Consortium
Open-Silicon is one of the founding members of the Hybrid Retention Cube consortium and is also the 1 that licenses the employ of the memory type. Specifically the difference betwixt HMC one.0 and HMC 2.0 include a bound from 15Gbit/south to 30Gbit/s (not the total constructive throughput of the HMC). Speeds upto 480GB/s are achievable with 1TB/s now in the horizon. The controller supports networking of upto 400Gb/s (increased form 100Gb/s). HMC is currently but bachelor in 2GB and 4Gb variants. Currently each HMC has 4 memory stacks with 1 control dice (similar to four+one or 4 Hi HBM) and TSVs are used to connect them.
"Stacked DRAM and logic solutions, such as HMC 2.0, pause through the retentiveness clogging and deliver the performance and low-power needed by side by side-generation computing systems," said Jim Handy, retention analyst with Objective Analysis. "Integration-ready interface solutions like Open-Silicon's HMC controller IP should drive down the cost of deployment, and advance this transition." The Open up-Silicon HMC 2.0 memory controller IP is a licensable, soft macro implementation that is designed to exist compliant with both HMC v1.0 and the upcoming HMC v2.0, supporting all of the defined data rates of both standards.
The device seamlessly interfaces to leading tertiary-party SerDes IP without the need for an additional PCS layer. Moreover, Open-Silicon'southward recently announced SerDes Engineering science Heart of Excellence (TCoE) volition provide ASIC customers a user-friendly and reliable manner to verify and test the integration of the HMC ii.0 memory controller IP with SerDes. Supporting data rates of upward to 480 GBytes/s, the IP offers a depression latency and a flexible user interface. The IP is delivered with a comprehensive set of deliverables including a test bench with a generic HMC model. For more information about the Open up-Silicon HMC 2.0 controller, delight visit http://www.open up-silicon.com/open-silicon-ips/hmc/ or e-mail united states at IP@open-silicon.com.
Needless to say this is merely one more than stride towards the mass implementation of the Hybrid Retentiveness Cube standard in everyday products. For the fourth dimension being still merely graphic and data accelerators are going to employ this with the mainstream segment occupied by JEDEC's High Bandwidth Memory. Nvidia and AMD are both going to be utilizing HBM in their futurity GPUs however professional accelerators such as Tesla might shift to HMC instead.
Source: https://wccftech.com/open-silicon-announces-worlds-hmc-20-controller-ip-partners-include-nvidia-intel/
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